ATA8742-PXQW【PDF 148/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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Sheet目录52

144页 145页 146页 147页 [148页]149页 150页 151页 152页

148

9151AINDCO07/09

ATA8742

executed. See the USISIF bit description in USISR USI Status Register on page 146 for fur-

ther details.

" Bit 6 USIOIE: Counter Overflow Interrupt Enable

Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt when

the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed.

See the USIOIF bit description in USISR USI Status Register on page 146 for further details.

" Bit 5..4 USIWM1..0: Wire Mode

These bits set the type of wire mode to be used. Basically only the function of the outputs are

affected by these bits. Data and clock inputs are not affected by the mode selected and will

always have the same function. The counter and Shift Register can therefore be clocked exter-

nally, and data input sampled, even when outputs are disabled. The relations between

USIWM1..0 and the USI operation is summarized in Table 23-1.

Note:

1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively

to avoid confusion between the modes of operation.

Table 23-1. Relations between USIWM1..0 and the USI Operation

USIWM1

USIWM0

Description

Outputs, clock hold, and start detector disabled. Port pins operates as

normal.

Three-wire mode. Uses DO, DI, and USCK pins.

The Data Output (DO) pin overrides the corresponding bit in the PORT

data direction. When the port pin is set as input the pins pull-up is controlled

by the PORT bit.

The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal

port operation. When operating as master, clock pulses are software

generated by toggling the PORT Register, while the data direction is set to

output. The USITC bit in the USICR Register can be used for this purpose.

Two-wire mode. Uses SDA (DI) and SCL (USCK) pins

(1)

The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and

uses open-collector output drives. The output drivers are enabled by setting

the corresponding bit for SDA and SCL in the DDR Register.

When the output driver is enabled for the SDA pin, the output driver will force

the line SDA low if the output of the Shift Register or the corresponding bit in

the PORT Register is zero. Otherwise the SDA line will not be driven (i.e., it is

released). When the SCL pin output driver is enabled the SCL line will be

forced low if the corresponding bit in the PORT Register is zero, or by the start

detector. Otherwise the SCL line will not be driven.

The SCL line is held low when a start detector detects a start condition and

the output is enabled. Clearing the Start Condition Flag (USISIF) releases the

line. The SDA and SCL pin inputs is not affected by enabling this mode.

Pull-ups on the SDA and SCL port pin are disabled in Two-wire mode.

Two-wire mode. Uses SDA and SCL pins.

Same operation as for the Two-wire mode described above, except that the

SCL line is also held low when a counter overflow occurs, and is held low until

the Counter Overflow Flag (USIOIF) is cleared.

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